This invention relates to cycle steal mechanisms for use in digital data processing systems for transferring data between a processor storage unit and a separate data handling unit. Though not limited thereto, the invention is particularly useful for cycle stealing data into or out of a microprocessor storage unit.
A data processing technique, which is frequently used, is known as "direct memory accessing". This enables an I/O unit to access the main storage unit of a host processor without requiring the attention of the host processor. Another technique that is in current usage is known as "cycle stealing". This is a technique used in some host processors for carrying out direct memory access operations. When a direct memory access request is received by the host processor from an I/O unit, one host processor clock cycle is "stolen" at the end of the "execute" portion of the current instruction. Typically, the entire data transfer to or from the host processor main storage unit takes place during the stolen host processor clock interval.
In various applications, it would be desirable to have a cycle stealing mechanism which did not have to wait until completion of the current instruction before gaining access to the storage unit. In particular, it would be desirable to be able to cycle steal the data to or from the storage unit during any of the various machine cycles which are involved in the fetching and execution of an instruction.
In general, the cycle stealing mechanisms heretofore proposed have been for enabling an I/O unit to cycle steal data into or out of a host processor main storage unit. In many present day applications, the I/O unit is coupled to the host processor by means of an I/O controller. Such I/O controller typically includes a microprocessor for supervising the data transfer activities. In such applications, it would frequently be desirable to have a reverse kind of cycle stealing mechanism for enabling the host processor to cycle steal data to or from the microprocessor storage unit located in the I/O controller. In such case, the host processor could cycle steal data into or out of the I/O controller storage unit at the same time that the I/O controller is busy cycle stealing a different set of data into or out of the host processor main storage unit. It would also be desirable to be able to do this reverse type of cycle stealing in a manner which is transparent to the microprocessor in the I/O controller.
There is described herein a new and improved cycle stealing mechanism which can be used to achieve one or more of the foregoing desirable objectives. While of general applicability, the invention is illustrated by means of an embodiment wherein the cycle stealing mechanism is used to enable a host processor to transfer data to or from a microprocessor storage unit located in an I/O controller in a manner which is transparent to the microprocessor.
For a better understanding of the present invention, together with other and further advantages and features thereof, reference is made to the following description taken in connection with the accompanying drawings, the scope of the invention being pointed out in the appended claims.